Low Power Application Specific Processing Element

Today the power consumption of integrated circuits (ICs) is considered as one of the most important problems for high performance chips. Many low power techniques have been proposed during the last 15 years [1]. In this paper the structure and instruction set of a processing element (PE), as a basic building block of complex ICs, is described. The micro-power PE’s model is described writing efficient register transfer logic (RTL) code from a lowpower standpoint using clock gating technique. The PE is implemented in FPGA technology. Simulation results show that power reduction of up to 10 times, in respect to standard PE design solutions, can be achieved using micro-power PE.